1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits. More particularly, the present invention relates to a multi-state read-only memory device and a method for fabricating the same.
2. Description of the Related Art
Read-only memory (ROM) semiconductor integrated circuits (IC) are widely used as memory storage devices for digital electronic equipment, in particular, microprocessor-based computer systems, to store predetermined programs. In a conventional semiconductor ROM device, the channel region of a memory cell is selectively implanted with ions to adjust the threshold voltage thereof depending on whether the programmed memory cell is turned on or turned off to represent a logic "1" or a logic "0" in binary, respectively. Conventional ROM IC devices, therefore, store a single binary bit in each of their memory cells. Then, conventional digital circuitry in the ROM employs sense amplifiers to sense the content of an addressed memory cell for "reading." The sensed result with respect to each memory cell within the ROM is identified as one of two possible electrical potential states. In other words, the memory content of a ROM memory cell as read is either a logic "1" or a logic "0."
The trend in the semiconductor industry has been to increase the number of memory cells to increase the storage capacity of a semiconductor integrated circuit chip, while reducing the size of the semiconductor device itself. Enlarged memory capacity and reduced memory semiconductor die size represent increased functionality and reduced cost, both of which are desirable qualities from a merchandising point of view. Great effort has been expended in the art of semiconductor chip manufacture to reduce the dimensions of semiconductor devices in order to squeeze more memory cells into the same semiconductor die area. This approach, however, is limited by the resolution available according to the current state of fabrication techniques.
Increasing the number of states to which a memory cell can correspond is a practicable means for overcoming present limitations. Consequently, a tri-state read-only memory is set forth, whose threshold voltage is adjusted through ion implantation with different dosages to be, for example, 5 V, 2.5 V, or 0.8 V, to have logic states designated as "1","-", or "0", respectively. Referring to FIG. 1, the top view of a conventional tri-state read-only memory device is depicted. Numerals 10 represent bit lines formed in a substrate 20 (will be described below) spaced apart in parallel along a first direction 100. Numerals 12 represent word lines striding over the bit lines 10 mutually spaced in parallel along a second direction 102, having a dielectric layer 21 (to be described below) therebelow for isolating them from the substrate 20, respectively. Two adjacent bit lines 10 and a word line 12 striding over them constitute the source/drain regions and gate electrode of a MOS transistor, respectively. The channel region of the MOS transistor for carrier transport is formed between the source/drain regions. Numerals 14 and 16 mark the channel regions for storing a first state. Numeral 18 marks the channel region for storing a second state, and the remaining channel regions act as the regions for storing a third state.
Next referring to FIGS. 2A-2C, a conventional process flow for fabricating the tri-state ROM device, depicted in FIG. 1, is shown in cross-sectional views. The left hand side of each drawing illustrates the cross-sectional view taken along a line A-A' shown in FIG. 1. The right hand side of each drawing illustrates the cross-sectional view taken along a line B-B' shown in FIG. 1.
The conventional method is suited to fabricate a tri-state ROM device on a semiconductor substrate 20. First, as shown in FIG. 2A, a plurality of bit lines 10 are formed by implanting ions into the substrate 20. For example, the substrate 20 is a p-type silicon substrate while the implanted ions are N-type impurities, such as phosphorus or arsenic ions. Therefore, the bit lines 10 are designated as BN.sup.+ buried in the substrate 20. Subsequently, thermal oxidation or deposition to the substrate 20 forms a silicon oxide layer acting as a dielectric layer 21, a polysilicon layer being thereafter formed on the dielectric layer 21, and then the polysilicon layer is etched to shape a plurality of word lines 12. As is known in this art, the polysilicon layer is doped with impurities so as to increase the conductivity thereof. After that, an oxide layer is deposited onto the overall surface, and then etched back to form spacers 22 on opposed sidewalls of the word lines 12.
Through a photolithography procedure, as shown in FIG. 2B, a first code mask layer 200 is formed over the substrate 20 to expose the channel regions for storing the first state, such as regions 14 and 16. By utilizing the first code mask layer 200 as an implantation mask, the impurities are implanted into the substrate 20 via the regions 14 and 16 to form first state region 23.
Whereby the first code mask layer 200 is thereafter removed and using another photolithography procedure, as shown in FIG. 2C, a second code mask layer 202 is formed over the substrate 20 for exposing the channel regions which stores the second state, such as the region 18. By utilizing the second code mask layer 202 as an implantation mask, the impurities are implanted into the substrate 20 via the region 18 to form a second state region 24. Because this ion implantation procedure makes use of a dosage higher than the aforementioned implantation procedure, the threshold voltages of these implanted channel regions 23 and 24 are adjusted into different states, such as 5 V and 2.5 V, respectively. The remaining channel regions are the regions for storing the third state, having a threshold voltage of about 0.8 V as exemplified.
The method for fabricating the tri-state ROM device utilizes multiple ion implantation procedures so as to program memory cells for storing one of the first, second, and third states. In such a way, the number of states which a memory cell can store is increased.
However, the conventional method is liable to incur misalignment problems resulting in inaccuracy while applying multiple photolithography procedures. For example, as shown in FIG. 3, numerals 30 are bit lines and numerals 32 represent word lines. Numerals 34 and 36 mark the channel regions for storing a first state. Numeral 38 marks the channel region for storing a second state, and the remaining channel regions act as the regions for storing a third state. In the drawing, the regions 36 and 38 are overlapped owing to misalignment problem revealing a overlapped region 39. Under this circumstance, the region 36 is affected by the high-dosage implantation procedure while implanting impurities via the region 38, resulting in a decreased current therein. Although the regions 36 and 34 belong to the same first state, the current flow therein varies.
For the forgoing reasons, there is a need for a method that can fabricate a multi-state ROM device without incurring misalignment problems.